參考來源：https://ghdl.readthedocs.io/en/latest/using/QuickStartGuide.html
先說載點：
ghdl:
https://ghdl.readthedocs.io/en/latest/getting/Releases.html
gtkwave:
https://sourceforge.net/projects/gtkwave/files/
然後根據ghdl的說明檔，先來實作一份加法器
ghdl quick start guide:
https://github.com/ghdl/ghdl/blob/master/doc/using/QuickStartGuide.rst#a-full-adder
步驟：
用文字編輯器撰寫vhdl
存檔並且副檔名為.vhd或是.vhdl
vhdl內的entity名稱不一定要與檔名一樣
先用ghdl -a [vhdl檔]
再用ghdl -e [entity名稱] ，elaborate這個entity但我不知道什麼是elaborate
最後ghdl -r [entity名稱]，跑這個vhdl，但是如果直接跑會沒有結果產生
因此需要製作testbench，testbench也是一段vhdl程式，他與一班vhdl差別在沒有port，是用來產生輸入信號以及檢查輸出是否為預期
重點：
vhdl檔案必須依照階層關係依序編譯，否則會造成頂端vhdl無法正確解譯
先用文字編輯器把下列程式存檔，檔名為「adder.vhdl」
entity adder is
-- `i0`, `i1`, and the carry-in `ci` are inputs of the adder.
-- `s` is the sum output, `co` is the carry-out.
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end adder;
architecture rtl of adder is
begin
-- This full-adder architecture contains two concurrent assignments.
-- Compute the sum.
s <= i0 xor i1 xor ci;
-- Compute the carry.
co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
end rtl;
接著把下列測試檔存檔，檔名為「adder_tb.vhdl」
-- A testbench has no ports.
entity adder_tb is
end adder_tb;
architecture behav of adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end component;
-- Specifies which entity is bound with the component.
for adder_0: adder use entity work.adder;
signal i0, i1, ci, s, co : bit;
begin
-- Component instantiation.
adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
s => s, co => co);
-- This process does the real job.
process
type pattern_type is record
-- The inputs of the adder.
i0, i1, ci : bit;
-- The expected outputs of the adder.
s, co : bit;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '0', '0'),
('0', '0', '1', '1', '0'),
('0', '1', '0', '1', '0'),
('0', '1', '1', '0', '1'),
('1', '0', '0', '1', '0'),
('1', '0', '1', '0', '1'),
('1', '1', '0', '0', '1'),
('1', '1', '1', '1', '1'));
begin
-- Check each pattern.
for i in patterns'range loop
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert s = patterns(i).s
report "bad sum value" severity error;
assert co = patterns(i).co
report "bad carry out value" severity error;
end loop;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
先用
ghdl -a adder.vhdl
再用
ghdl -a adder_tb.vhdl
ghdl -e adder_tb
最後
ghdl -r adder_tb --vcd=adder.vcd
結果會在檔案所在資料夾中看到一個名為adder.vcd的檔案，點開來會自動啟動gtkwave
看到以下畫面：
先在左上的adder_0點一下，接著到左下幾個reg ...都點兩下，結果會在右側波形視窗出現綠線
接著用放大鏡-，一直按一直按，隨著時間刻度慢慢放大，大概到ns間距時，波形開始出現
